Thursday , October 21 2021

AMD EPYC Generation 2 Server Processors Receive Up to 256MB L3 Cache



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Next year, AMD intends to launch a 7-nm EPYC server processor in Zen 2 architecture, an official announcement that took place half a month ago. The two-socket system based on a pair of flagship 64-core engineering samples was recently spotted in the SiSoftware Sandra test database, thereby shedding light on the technical characteristics of the upcoming CPU.

AMD EPYC Rome

Remember the second generation AMD EPYC processor is a multi-chip module, which is assembled with eight 7-nm "chiplets", each of which contains eight Zen 2 cores and a 14-nm I / O chip that contains an eight-channel DDR4 memory controller and interface controller PCI Express 4.0 and other peripherals.

AMD EPYC Rome

According to records in the SiSoftware database, each "chiplets" will immediately contain 32 MB of cache at the third level, divided equally between two four core CCX units. In other words, the L3 cache volume when moving from Zen / Zen + architecture to Zen 2 will grow exactly twice. The third level cache in the AMD EPYC 64-core is 256 MB which is impressive.

AMD EPYC

As for the work frequency, seen from the designation 2S1404E2VJUG5_20 / 14_N, the sample is seen in the SiSoftware function at a nominal speed of 1.4 GHz, and in boost mode it can accelerate up to 2 GHz. Note that releasing the frequency must grow to 2.35 GHz.

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