Little information upfront: What is called Intel Xe aka Gen12 is the architecture for the first dedicated and modern graphics chip since i740 1998. Several models are currently under development, at least some of which are DG1 (Discrete Graphic 1) aka Arctic Sound aka Arctic Sound aka Arctic Sound executable silicon exists. For supercomputers, Intel is developing a 7-nm branch, this brings Ponte Vecchio as a code name and is at the upcoming Aurora, the first Exaflops supercomputer in the US.
At the 2019 Supercomputer in Denver, USA, Intel has mentioned some details about Aurora and Ponte Vecchio: This system is expected to reach more than one Exaflops and is being developed on behalf of the Department of Energy (DoE) to be commissioned in 2021 at the Argonne National Laboratory in Chicago. Each Aurora compute node consists of six 7nm Xe accelerators and two Xeon CPUs, where Intel uses Sapphire Rapids with production of 10 ++ nm. The processor connects DDR5 memory and Optane Memory which is not volatile.
Each Ponte Vecchio can communicate directly with each Ponte Vecchio, Intel uses the Compute Express Link (CXL) version to connect the Sapphire cache coherently with the 7-nm Xe accelerator. Based on the combination of 2.5D and 3D packaging, more specifically EMIB (Embedded Multi The Interconnect Bridge) and Intel's Foveros. In early July 2019, Intel demonstrated how this could look like a design based on HBM2 memory stacks and some dead logic on one operator. For Ponte Vecchio, manufacturers generally talk about packet cache very much and very quickly, indicating HBM2E or HBM3.
Other features of Xe for supercomputers include Intel, but the chip will have much-needed support for the HPC segment for high-speed double-precision calculation (FP64). In addition, there are flexible matrix and vector machines, so here Intel tends to speed up typical algorithms for machine learning in hardware. Aurora runs the Intel OneAPI software stack, which handles CPUs via FPGA and GPUs of all types of accelerators.